26 cout <<
"VerilogDataBase::" << __func__ << endl;
37 cout << __func__ <<
" => " << module_name <<
"\n";
38 for (std::vector<VerilogParser::GeneralName>::const_iterator it = vPinName.begin(); it != vPinName.end(); ++it)
39 cout <<
"\t" << it->name <<
"[" << it->range.low <<
":" << it->range.high <<
"] ";
51 virtual void verilog_instance_cbk(std::string
const& macro_name, std::string
const& inst_name, std::vector<VerilogParser::NetPin>
const& vNetPin)
53 cout << __func__ <<
" => " << macro_name <<
", " << inst_name <<
", ";
54 for (std::vector<VerilogParser::NetPin>::const_iterator it = vNetPin.begin(); it != vNetPin.end(); ++it)
56 if (it->net ==
"VerilogParser::CONSTANT_NET")
58 cout << it->pin <<
"(" << it->net <<
" " << it->extension.constant <<
")" <<
"[" << it->range.low <<
":" << it->range.high <<
"] ";
60 else if (it->net ==
"VerilogParser::GROUP_NETS")
62 cout << it->pin <<
"(" << it->net <<
" {";
63 for (std::vector<VerilogParser::GeneralName>::const_iterator itn = it->extension.vNetName->begin(); itn != it->extension.vNetName->end(); ++itn)
65 cout <<
"(" << itn->name <<
")" <<
"[" << itn->range.low <<
":" << itn->range.high <<
"] ";
67 cout <<
"} " <<
")" <<
"[" << it->range.low <<
":" << it->range.high <<
"] ";
71 cout << it->pin <<
"(" << it->net <<
")" <<
"[" << it->range.low <<
":" << it->range.high <<
"] ";
84 cout << __func__ <<
" => " << net_name <<
" (" << range.
low <<
", " << range.
high <<
")" << endl;
95 cout << __func__ <<
" => " << pin_name <<
" " << type <<
" (" << range.
low <<
", " << range.
high <<
")" << endl;
107 cout << __func__ <<
" => " << target_name <<
" (" << target_range.
low <<
", " << target_range.
high <<
")" <<
" = "
108 << source_name <<
" (" << source_range.
low <<
", " << source_range.
high <<
")" << endl;
115 cout <<
"////////////// test1 ////////////////" << endl;
123 cout <<
"////////////// test2 ////////////////" << endl;
136 int main(
int argc,
char** argv)
145 cout <<
"at least 1 argument is required" << endl;
virtual void verilog_instance_cbk(std::string const ¯o_name, std::string const &inst_name, std::vector< VerilogParser::NetPin > const &vNetPin)
read an instance.
range with pair of low and high values
Custom class that inheritates VerilogParser::VerilogDataBase with all the required callbacks defined...
virtual void verilog_net_declare_cbk(std::string const &net_name, VerilogParser::Range const &range)
read an net declaration
virtual void verilog_module_declaration_cbk(std::string const &module_name, std::vector< VerilogParser::GeneralName > const &vPinName)
read a module declaration
Driver for Verilog parser.
int low
low value, min infinity if not specified
void test2(string const &filename)
test 2: use class wrapper BookshelfParser::Driver
bool parse_file(const string &filename)
bool read(VerilogDataBase &db, const string &verilogFile)
API for VerilogParser. Read Verilog file and initialize database by calling user-defined callback fun...
virtual void verilog_assignment_cbk(std::string const &target_name, VerilogParser::Range const &target_range, std::string const &source_name, VerilogParser::Range const &source_range)
read an assignment
void test1(string const &filename)
test 1: use function wrapper BookshelfParser::read
VerilogDataBase()
constructor
int main(int argc, char **argv)
main function
virtual void verilog_pin_declare_cbk(std::string const &pin_name, unsigned type, VerilogParser::Range const &range)
read an pin declaration
Base class for verilog database. Only pure virtual functions are defined. User needs to inheritate th...