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VerilogParser::VerilogDataBase Class Referenceabstract

Base class for verilog database. Only pure virtual functions are defined. User needs to inheritate this class and derive a custom database type with all callback functions defined. More...

#include <VerilogDataBase.h>

Inheritance diagram for VerilogParser::VerilogDataBase:
VerilogDataBase

Public Member Functions

virtual void verilog_module_declaration_cbk (std::string const &module_name, std::vector< GeneralName > const &vPinName)
 read a module declaration More...
 
virtual void verilog_instance_cbk (std::string const &macro_name, std::string const &inst_name, std::vector< NetPin > const &vNetPin)=0
 read an instance. More...
 
virtual void verilog_net_declare_cbk (std::string const &net_name, Range const &range)=0
 read an net declaration More...
 
virtual void verilog_pin_declare_cbk (std::string const &pin_name, unsigned type, Range const &range)=0
 read an pin declaration More...
 
virtual void verilog_assignment_cbk (std::string const &target_name, Range const &target_range, std::string const &source_name, Range const &source_range)
 read an assignment More...
 

Protected Member Functions

void verilog_user_cbk_reminder (const char *str) const
 remind users to define some optional callback functions at runtime More...
 

Detailed Description

Base class for verilog database. Only pure virtual functions are defined. User needs to inheritate this class and derive a custom database type with all callback functions defined.

Definition at line 211 of file VerilogDataBase.h.

Member Function Documentation

virtual void VerilogParser::VerilogDataBase::verilog_assignment_cbk ( std::string const &  target_name,
Range const &  target_range,
std::string const &  source_name,
Range const &  source_range 
)
virtual

read an assignment

assign exu_mmu_early_va_e[0] = exu_mmu_early_va_e[0];

Parameters
target_namename of left hand side
target_rangerange of left hand side, negative infinity if either low or high value of the range is not defined
source_namename of right hand side
source_rangerange of right hand side, negative infinity if either low or high value of the range is not defined

Reimplemented in VerilogDataBase.

virtual void VerilogParser::VerilogDataBase::verilog_instance_cbk ( std::string const &  macro_name,
std::string const &  inst_name,
std::vector< NetPin > const &  vNetPin 
)
pure virtual

read an instance.

NOR2_X1 u2 ( .a(n1), .b(n3), .o(n2) ); NOR2_X1 u2 ( .a(n1), .b({n3, n4}), .o(n2) ); NOR2_X1 u2 ( .a(n1), .b(1'b0), .o(n2) );

Parameters
macro_namestandard cell type or module name
inst_nameinstance name
vNetPinarray of pairs of net and pin

Implemented in VerilogDataBase.

virtual void VerilogParser::VerilogDataBase::verilog_module_declaration_cbk ( std::string const &  module_name,
std::vector< GeneralName > const &  vPinName 
)
virtual

read a module declaration

module NOR2_X1 ( a, b, c );

Parameters
module_namename of a module
vPinNamearray of pins

Reimplemented in VerilogDataBase.

virtual void VerilogParser::VerilogDataBase::verilog_net_declare_cbk ( std::string const &  net_name,
Range const &  range 
)
pure virtual

read an net declaration

wire aaa[1];

Parameters
net_namenet name
rangenet range, negative infinity if either low or high value of the range is not defined

Implemented in VerilogDataBase.

virtual void VerilogParser::VerilogDataBase::verilog_pin_declare_cbk ( std::string const &  pin_name,
unsigned  type,
Range const &  range 
)
pure virtual

read an pin declaration

input inp2;

Parameters
pin_namepin name
typetype of pin, refer to VerilogParser::PinType
rangepin range, negative infinity if either low or high value of the range is not defined

Implemented in VerilogDataBase.

void VerilogParser::VerilogDataBase::verilog_user_cbk_reminder ( const char *  str) const
protected

remind users to define some optional callback functions at runtime

Parameters
strmessage including the information to the callback function in the reminder

The documentation for this class was generated from the following file: