Limbo.Parsers.VerilogParser

Table of Contents

• Introduction
• Examples
  • Flex/Bison Parser
  • All Examples
• References

Introduction

Verilog is a hardware programming language. In VLSI design, after logic synthesis, the circuit is converted from behavior level description to gate level netlist, which will be used in physical design. The parser supports reading the gate level netlists to help users initialize their databases.

Examples

Flex/Bison Parser

See documented version: test/parsers/verilog/test_bison.cpp

#include <iostream>
#include <fstream>

#include <limbo/parsers/verilog/bison/VerilogDriver.h>

using std::cout;
using std::cin;
using std::endl;
using std::string;

class VerilogDataBase : public VerilogParser::VerilogDataBase
{
    public:
        VerilogDataBase()
        {
            cout << "VerilogDataBase::" << __func__ << endl;
        }
        virtual void verilog_module_declaration_cbk(std::string const& module_name, std::vector<VerilogParser::GeneralName> const& vPinName)
        {
            cout << __func__ << " => " << module_name << "\n";
            for (std::vector<VerilogParser::GeneralName>::const_iterator it = vPinName.begin(); it != vPinName.end(); ++it)
                cout << "\t" << it->name << "[" << it->range.low << ":" << it->range.high << "] ";
            cout << endl; 
        }
        virtual void verilog_instance_cbk(std::string const& macro_name, std::string const& inst_name, std::vector<VerilogParser::NetPin> const& vNetPin)
        {
            cout << __func__ << " => " << macro_name << ", " << inst_name << ", ";
            for (std::vector<VerilogParser::NetPin>::const_iterator it = vNetPin.begin(); it != vNetPin.end(); ++it)
            {
                if (it->net == "VerilogParser::CONSTANT_NET")
                {
                    cout << it->pin << "(" << it->net << " " << it->extension.constant << ")" << "[" << it->range.low << ":" << it->range.high << "] ";
                }
                else if (it->net == "VerilogParser::GROUP_NETS")
                {
                    cout << it->pin << "(" << it->net << " {";
                    for (std::vector<VerilogParser::GeneralName>::const_iterator itn = it->extension.vNetName->begin(); itn != it->extension.vNetName->end(); ++itn)
                    {
                        cout << "(" << itn->name << ")" << "[" << itn->range.low << ":" << itn->range.high << "] ";
                    }
                    cout << "} " << ")" << "[" << it->range.low << ":" << it->range.high << "] ";
                }
                else 
                {
                    cout << it->pin << "(" << it->net << ")" << "[" << it->range.low << ":" << it->range.high << "] ";
                }
            }
            cout << endl;
        }
        virtual void verilog_net_declare_cbk(std::string const& net_name, VerilogParser::Range const& range)
        {
            cout << __func__ << " => " << net_name << " (" << range.low << ", " << range.high << ")" << endl;
        }
        virtual void verilog_pin_declare_cbk(std::string const& pin_name, unsigned type, VerilogParser::Range const& range)
        {
            cout << __func__ << " => " << pin_name << " " << type << " (" << range.low << ", " << range.high << ")" << endl;
        }
        virtual void verilog_assignment_cbk(std::string const& target_name, VerilogParser::Range const& target_range, std::string const& source_name, VerilogParser::Range const& source_range)
        {
            cout << __func__ << " => " << target_name << " (" << target_range.low << ", " << target_range.high << ")" << " = " 
                << source_name << " (" << source_range.low << ", " << source_range.high << ")" << endl;
        }
};

void test1(string const& filename)
{
    cout << "////////////// test1 ////////////////" << endl;
    VerilogDataBase db;
    VerilogParser::read(db, filename);
}

void test2(string const& filename)
{
    cout << "////////////// test2 ////////////////" << endl;
    VerilogDataBase db;
    VerilogParser::Driver driver (db);
    //driver.trace_scanning = true;
    //driver.trace_parsing = true;

    driver.parse_file(filename);
}

int main(int argc, char** argv)
{

    if (argc > 1)
    {
        test1(argv[1]);
        test2(argv[1]);
    }
    else 
        cout << "at least 1 argument is required" << endl;

    return 0;
}

Compiling and running commands (assuming LIMBO_DIR is exported as the environment variable to the path where limbo library is installed)

g++ -o test_bison test_bison.cpp -I $LIMBO_DIR/include -L $LIMBO_DIR/lib -lverilogparser
./test_bison benchmarks/simple.v

All Examples

• test/parsers/verilog/test_bison.cpp

References

• limbo/parsers/verilog/bison/VerilogDataBase.h
• limbo/parsers/verilog/bison/VerilogDriver.h