We present a high performance MPL-Decomposer to resolve the layout decomposition problem for multiple patterning lithography.
As the minimum feature size further decreases, multiple patterning lithography (MPL) has become one of the most viable solutions to sub-14nm half-pitch patterning. Multiple patterning lithography consists of double, triple, or quadruple patterning. In multiple patterning lithography manufacturing process, there are several exposure/etching steps, through which the layout can be produced. The advantage of this process is that the effective pitch can be improved, which improves the lithography resolution.
The key challenge of multiple patterning lithography is the layout decomposition, where input layout is divided into several masks. When the distance between two input features is less than minimum coloring distance, they need to be assigned to different masks to avoid a coloring conflict. Sometimes coloring conflict can be also resolved by inserting stitch to split a pattern into two touching parts. However this introduces stitches, which lead to yield loss because of overlay error. Therefore, two of the main objectives in layout decomposition are conflict minimization and stitch minimization.