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We present a high performance MPL-Decomposer to resolve the layout decomposition problem for multiple patterning lithography.
We present TPLPlace, a triple patterning lithography aware detailed placement solver.
We present DFI, a fill optimization framework with multiple objectives and constraints.
We present MrDP, a detailed placer that can handle multiple-row height cells in designs.
We present OpenMPL, an open-source multiple patterning layout decomposition framework for advanced multiple patterning lithography.
We present DREAMPlace, a deep learning toolkit-enabled VLSI placement framework. With the analogy between nonlinear VLSI placement and deep learning training problem, this tool is developed with deep learning toolkit for flexibility and efficiency. The tool runs on both CPU and GPU. Over 30X speedup over the CPU implementation (RePlAce) is achieved in global placement and legalization on ISPD 2005 contest benchmarks with a Nvidia Tesla V100 GPU.